The following DSP Cores have a built-in 4ch/4ch Dante interface.
The Dante signal is available on the ETH
port on the rear of the DSP core.
Each of these cores and the 52-7310A 52/XC2 Concentrator have an additional expansion slot. You can insert there a 52-7080 XC2 Dante IP audio interface.
The following table shows the factory settings for the Dante interfaces in DHD devices. You can change the parameters in Dante Controller - Device View - Network Config tab.
interface type | module | IP Address setting | Switch Configuration |
---|---|---|---|
built in 4ch/4ch Dante interface | 52-7420A, 52-7423A, 52-7410A, 52-1810A, 52-1830A | Obtain an IP Address Automatically | not available |
built in 64ch/64ch Dante interface | 52-7080A | Obtain an IP Address Automatically | redundant |
48ch/48ch Dante interface | 52-7180A | Obtain an IP Address Automatically | redundant |
You can add a Dante device in TB8 via I/O Overview menu. Click Add
and select your type of Dante device. If your core device is equipped with a Dante 4×4 interface, the I/Os of it are added automatically when you add your core device. It is named “<Core Name>.Dante” by default.
For more information on adding and using I/O units, see Toolbox8 Documentation - I/O Overview.
General recommendations:
Note
The AES67 option for supported DHD Dante Modules is available since Dante software version 3.9.6.1.
Updates for DHD's Dante modules are directly provided by DHD.
Important
The 4ch/4ch Dante interface in 52/XC2 and 52/XS2 cores does not support AES67.
Dante uses the Precision_Time_Protocol (PTP) in version 1 (IEEE 1588-2002).
Dante supports PTP version 2 (IEEE 1588-2008), when the AES67 mode is enabled.
If you enable the AES67 support on a Dante device, it enables both IEEE PTP v1 and v2. A single clock domain exists across both PTP v1 and v2 devices:
One AES67-enabled Dante device will act as a boundary clock between PTP v1 and v2, bridging the two clock domains. Additional clocking status information is available in Dante Controller for PTP v2 clocking.